Graduate School of Science and Technology, Keio University
Graduate School of Science and Technology, Keio University
Department of Electrical and Electronics Engineering, University of the Ryukyus
Numerical Simulation Research Group, Institute of Aeronautical Technology, Japan Aerospace Exploration Agency (JAXA)
Graduate School of Science and Technology, Keio University
出版者
電子情報通信学会
出版者（英）
The Institute of Electronics, Information and Communication Engineers
雑誌名
IEICE TRANSACTIONS on Information and Systems
巻
E95-D
号
10
ページ
2369 - 2376
発行年
2012-10-01
抄録（英）
Computational Fluid Dynamics (CFD) is used as a common design tool in the aerospace industry. UPACS, a package for CFD, is convenient for users, since a customized simulator can be built just by selecting desired functions. The problem is its computation speed, which is difficult to enhance by using the clusters due to its complex memory access patterns. As an economical solution, accelerators using FPGAs are hopeful candidate. However, the total scale of UPACS is too large to be implemented on small numbers of FPGAs. For cost efficient implementation, partial reconfiguration which dynamically loads only required functions is proposed in this paper. Here, the MUSCL scheme, which is used frequently in UPACS, is selected as a target. Partial reconfiguration is applied to the flux limiter functions (FLF) in MUSCL. Four FLFs are implemented for Turbulence MUSCL (TMUSCL) and eight FLFs are for Convection MUSCL (CMUSCL). All FLFs are developed independently and separated from the top MUSCL module. At start-up, only required FLFs are selected and deployed in the system without interfering the other modules. This implementation has successfully reduced the resource utilization by 44% to 63%. Total power consumption also reduced by 33%. Configuration speed is improved by 34-times faster as compared to full reconfiguration method. All implemented functions achieved at least 17 times speed-up performance compared with the software implementation.
Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA
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