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24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%
https://jaxa.repo.nii.ac.jp/records/39546
https://jaxa.repo.nii.ac.jp/records/39546d22d3eb9-edcf-44f0-85bf-2189b75e30d6
Item type | 会議発表論文 / Conference Paper(1) | |||||
---|---|---|---|---|---|---|
公開日 | 2015-08-28 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | 24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60% | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
資源タイプ | conference paper | |||||
アクセス権 | ||||||
アクセス権 | metadata only access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_14cb | |||||
著者 |
Kosuge, Atsutake
× Kosuge, Atsutake× Ishizuka, Shu× Abe, Mami× Ichikawa, Satoshi× Kuroda, Tadahiro |
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著者所属(英) | ||||||
en | ||||||
Keio University | ||||||
著者所属(英) | ||||||
en | ||||||
Keio University | ||||||
著者所属(英) | ||||||
en | ||||||
Japan Aerospace Exploration Agency (JAXA) | ||||||
著者所属(英) | ||||||
en | ||||||
Japan Aerospace Exploration Agency (JAXA) | ||||||
著者所属(英) | ||||||
en | ||||||
Keio University | ||||||
出版者(英) | ||||||
出版者 | Institute of Electrical and Electronics Engineers, Inc.(IEEE) | |||||
書誌情報 |
en : Solid- State Circuits Conference - (ISSCC), 2015 IEEE International p. 1-3, 発行日 2015-02 |
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会議概要(会議名, 開催地, 会期, 主催者等)(英) | ||||||
内容記述タイプ | Other | |||||
内容記述 | Solid- State Circuits Conference - (ISSCC), 2015 IEEE International (February 22-26, 2015.), San Francisco, CA, USA | |||||
抄録(英) | ||||||
内容記述タイプ | Other | |||||
内容記述 | Processor systems that are mounted in satellites must be small and light, having high data transfer rates, and high storage capacity [1]. A small reduction in size and weight could reduce the cost of launching a satellite by a significant amount. The next generation of earth observation satellites will require data transmission rates to a maximum of 20Gb/s and at least one terabyte of storage capacity. The volume, weight, and communication speed of the processor system is determined by the backplane connectors (Fig. 20.4.1). It is difficult to achieve a connector that can pass signals of 2.5Gb/s or more. The signal reflection that occurs when signals are branched at connectors and at the wire stubs of branches decreases the transmission speed, so only point-to-point connections are possible. Once the satellite is launched, repair or replacement is not possible, and system redundancy is introduced. Accordingly, 512 backplane wires would be required. The signal connector would require 1,024pins, including the ground pins used to prevent crosstalk, and would be 512mm wide, which is even wider than the circuit board of each module. | |||||
ISBN | ||||||
識別子タイプ | ISBN | |||||
関連識別子 | 978-1-4799-6223-5 | |||||
DOI | ||||||
識別子タイプ | DOI | |||||
関連識別子 | http://dx.doi.org/10.1109/ISSCC.2015.7063112 | |||||
関連名称 | info:doi/10.1109/ISSCC.2015.7063112 | |||||
資料番号 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 資料番号: PA1510077000 |