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Applicability of redundant pairs of SOI transistors for analog circuits
https://jaxa.repo.nii.ac.jp/records/4320
https://jaxa.repo.nii.ac.jp/records/43209fabe3c5-bb7c-46d0-9574-f06725798381
名前 / ファイル | ライセンス | アクション |
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61889026.pdf (292.5 kB)
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Item type | 会議発表論文 / Conference Paper(1) | |||||
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公開日 | 2015-03-26 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Applicability of redundant pairs of SOI transistors for analog circuits | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | SOI | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | Phase-Locked Loop | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | Radiation Hardness-By-Design | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
資源タイプ | conference paper | |||||
著者 |
Makihara, A.
× Makihara, A.× Yokose, T.× Tsuchiya, Y.× Tani, K.× Morimura, T.× Abe, H.× Shindo, H.× Ebihara, T.× Maru, A.× Morikawa, K.× Kuboyama, S.× Tamura, T.× Makihara, A.× Yokose, T.× Tsuchiya, Y.× Tani, K.× Morimura, T.× Abe, H.× Shindo, H.× Ebihara, T.× Maru, A.× Morikawa, K.× Kuboyama, S.× Tamura, T. |
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著者所属 | ||||||
HIREC株式会社 | ||||||
著者所属 | ||||||
HIREC株式会社 | ||||||
著者所属 | ||||||
HIREC株式会社 | ||||||
著者所属 | ||||||
HIREC株式会社 | ||||||
著者所属 | ||||||
HIREC株式会社 | ||||||
著者所属 | ||||||
日本原子力研究開発機構(JAEA) | ||||||
著者所属 | ||||||
宇宙航空研究開発機構(JAXA) | ||||||
著者所属 | ||||||
宇宙航空研究開発機構(JAXA) | ||||||
著者所属 | ||||||
宇宙航空研究開発機構(JAXA) | ||||||
著者所属 | ||||||
宇宙航空研究開発機構(JAXA) | ||||||
著者所属 | ||||||
宇宙航空研究開発機構(JAXA) | ||||||
著者所属 | ||||||
宇宙航空研究開発機構(JAXA) | ||||||
著者所属(英) | ||||||
en | ||||||
High-Reliability Engineering & Components Corporation (HIREC) | ||||||
著者所属(英) | ||||||
en | ||||||
High-Reliability Engineering & Components Corporation (HIREC) | ||||||
著者所属(英) | ||||||
en | ||||||
High-Reliability Engineering & Components Corporation (HIREC) | ||||||
著者所属(英) | ||||||
en | ||||||
High-Reliability Engineering & Components Corporation (HIREC) | ||||||
著者所属(英) | ||||||
en | ||||||
High-Reliability Engineering & Components Corporation (HIREC) | ||||||
著者所属(英) | ||||||
en | ||||||
Japan Atomic Energy Agency (JAEA) | ||||||
著者所属(英) | ||||||
en | ||||||
Japan Aerospace Exploration Agency (JAXA) | ||||||
著者所属(英) | ||||||
en | ||||||
Japan Aerospace Exploration Agency (JAXA) | ||||||
著者所属(英) | ||||||
en | ||||||
Japan Aerospace Exploration Agency (JAXA) | ||||||
著者所属(英) | ||||||
en | ||||||
Japan Aerospace Exploration Agency (JAXA) | ||||||
著者所属(英) | ||||||
en | ||||||
Japan Aerospace Exploration Agency (JAXA) | ||||||
著者所属(英) | ||||||
en | ||||||
Japan Aerospace Exploration Agency (JAXA) | ||||||
出版者 | ||||||
出版者 | 宇宙航空研究開発機構(JAXA) | |||||
出版者(英) | ||||||
出版者 | Japan Aerospace Exploration Agency (JAXA) | |||||
書誌情報 |
宇宙航空研究開発機構特別資料 en : JAXA Special Publication 巻 JAXA-SP-12-008E, p. 123-126, 発行日 2013-03-29 |
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抄録(英) | ||||||
内容記述タイプ | Other | |||||
内容記述 | Redundant pairs of SOI transistors have been utilized as a Radiation Hardening-By-Design technique and their applicability was subsequently extended for analog circuits. In this paper, the principle of the SET free inverter (SFI) operation is extended to analog circuits such as current mirror circuits and has been successfully demonstrated with a phase-locked loop circuit intended for use in ASICs, which includes some analog circuit blocks, such as the current mirror, differential amplifiers and so on. | |||||
内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 形態: カラー図版あり | |||||
内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 著者人数: 12名 | |||||
内容記述(英) | ||||||
内容記述タイプ | Other | |||||
内容記述 | Physical characteristics: Original contains color illustrations | |||||
内容記述(英) | ||||||
内容記述タイプ | Other | |||||
内容記述 | Number of authors: 12 | |||||
ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 1349-113X | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA11984031 | |||||
資料番号 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 資料番号: AA0061889026 | |||||
レポート番号 | ||||||
内容記述タイプ | Other | |||||
内容記述 | レポート番号: JAXA-SP-12-008E |