{"created":"2023-06-20T14:54:04.283914+00:00","id":22311,"links":{},"metadata":{"_buckets":{"deposit":"f267c849-fd90-4220-9efa-2cdb5886d01d"},"_deposit":{"created_by":1,"id":"22311","owners":[1],"pid":{"revision_id":0,"type":"depid","value":"22311"},"status":"published"},"_oai":{"id":"oai:jaxa.repo.nii.ac.jp:00022311","sets":["1887:1888"]},"author_link":["209053","209060","209057","209054","209058","209061","209055","209056","209059","209052"],"item_7_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2012-10-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"10","bibliographicPageEnd":"2376","bibliographicPageStart":"2369","bibliographicVolumeNumber":"E95-D","bibliographic_titles":[{},{"bibliographic_title":"IEICE TRANSACTIONS on Information and Systems","bibliographic_titleLang":"en"}]}]},"item_7_description_17":{"attribute_name":"抄録（英）","attribute_value_mlt":[{"subitem_description":"Computational Fluid Dynamics (CFD) is used as a common design tool in the aerospace industry. UPACS, a package for CFD, is convenient for users, since a customized simulator can be built just by selecting desired functions. The problem is its computation speed, which is difficult to enhance by using the clusters due to its complex memory access patterns. As an economical solution, accelerators using FPGAs are hopeful candidate. However, the total scale of UPACS is too large to be implemented on small numbers of FPGAs. For cost efficient implementation, partial reconfiguration which dynamically loads only required functions is proposed in this paper. Here, the MUSCL scheme, which is used frequently in UPACS, is selected as a target. Partial reconfiguration is applied to the flux limiter functions (FLF) in MUSCL. Four FLFs are implemented for Turbulence MUSCL (TMUSCL) and eight FLFs are for Convection MUSCL (CMUSCL). All FLFs are developed independently and separated from the top MUSCL module. At start-up, only required FLFs are selected and deployed in the system without interfering the other modules. This implementation has successfully reduced the resource utilization by 44% to 63%. Total power consumption also reduced by 33%. Configuration speed is improved by 34-times faster as compared to full reconfiguration method. All implemented functions achieved at least 17 times speed-up performance compared with the software implementation.","subitem_description_type":"Other"}]},"item_7_description_32":{"attribute_name":"資料番号","attribute_value_mlt":[{"subitem_description":"資料番号: PA1210022000","subitem_description_type":"Other"}]},"item_7_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"電子情報通信学会"}]},"item_7_publisher_9":{"attribute_name":"出版者（英）","attribute_value_mlt":[{"subitem_publisher":"The Institute of Electronics, Information and Communication Engineers"}]},"item_7_relation_25":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"info:doi/10.1587/transinf.E95.D.2369"}],"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"http://dx.doi.org/10.1587/transinf.E95.D.2369","subitem_relation_type_select":"DOI"}}]},"item_7_rights_28":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"(C)2012 The Institute of Electronics, Information and Communication Engineers"}]},"item_7_source_id_21":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0916-8532","subitem_source_identifier_type":"ISSN"}]},"item_7_source_id_22":{"attribute_name":"ISSNONLINE","attribute_value_mlt":[{"subitem_source_identifier":"1745-1361","subitem_source_identifier_type":"ISSN"}]},"item_7_source_id_24":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA10826272","subitem_source_identifier_type":"NCID"}]},"item_7_text_6":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"},{"subitem_text_value":"琉球大学工学部電気電子工学科"},{"subitem_text_value":"宇宙航空研究開発機構航空本部数値解析技術研究グループ(JAXA)"},{"subitem_text_value":"慶應義塾大学大学院理工学研究科"}]},"item_7_text_7":{"attribute_name":"著者所属（英）","attribute_value_mlt":[{"subitem_text_language":"en","subitem_text_value":"Graduate School of Science and Technology, Keio University"},{"subitem_text_language":"en","subitem_text_value":"Graduate School of Science and Technology, Keio University"},{"subitem_text_language":"en","subitem_text_value":"Department of Electrical and Electronics Engineering, University of the Ryukyus"},{"subitem_text_language":"en","subitem_text_value":"Numerical Simulation Research Group, Institute of Aeronautical Technology, Japan Aerospace Exploration Agency (JAXA)"},{"subitem_text_language":"en","subitem_text_value":"Graduate School of Science and Technology, Keio University"}]},"item_7_version_type_30":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Abu, Talip  Mohamad Sofian"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"赤嶺, 高之"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"長名, 保範"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"藤田, 直行"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Abu, Talip  Mohamad Sofian","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Akamine, Takayuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Osana, Yasunori","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Fujita, Naoyuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Amano, Hideharu","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-01-22"}],"displaytype":"detail","filename":"PA2012022.pdf","filesize":[{"value":"693.6 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"PA2012022.pdf","url":"https://jaxa.repo.nii.ac.jp/record/22311/files/PA2012022.pdf"},"version_id":"e66da8af-ff23-4d37-9adb-a67555422393"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"computational fluid dynamics (CFD)","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"field programmable gate array (FPGA)","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"scientific computations","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"reconfigurable hardware","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"partial reconfiguration","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA","subitem_title_language":"en"}]},"item_type_id":"7","owner":"1","path":["1888"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-03-26"},"publish_date":"2015-03-26","publish_status":"0","recid":"22311","relation_version_is_last":true,"title":["Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA"],"weko_creator_id":"1","weko_shared_id":-1},"updated":"2023-06-21T03:23:12.480884+00:00"}