@techreport{oai:jaxa.repo.nii.ac.jp:00002765,
 author = {池田, 直美 and 新藤, 浩之 and 飯出, 芳弥 and 浅井, 弘彰 and 久保山, 智司 and 松田, 純夫 and Ikeda, Naomi and Shindo, Hiroyuki and Iide, Yoshiya and Asai, Hiroaki and Kuboyama, Satoshi and Matsuda, Sumio},
 month = {Feb},
 note = {Seven kinds of COTS memories were installed in Commercial Semiconductor Devices (CSD) and their single event effects were observed. Single Event Upset (SEU) and Multi-Bit Upset (MBU) were observed in DRAMs and SRAMs, and no Single Event Latchup (SEL) was observed in all memories. The results showed that most of SEU and MBU was caused by protons in Van Allen belt, and that the number of MBU was considerably large to neglect. They also showed that some of the on-orbit data were not consistent with the results obtained from the ground test. This implies that the structure of recent memories have become too small to predict accurate SEU rate by present model., 資料番号: AA0046975005, レポート番号: JAXA-RM-03-022},
 title = {MDS-1(つばさ)搭載民生用メモリ素子のシングルイベント効果に関する解析結果},
 year = {2004}
}