@inproceedings{oai:jaxa.repo.nii.ac.jp:00003486,
 author = {高木, 亮治 and 杉崎, 由典 and 鈴木, 清文 and Takaki, Ryoji and Sugisaki, Yoshinori and Suzuki, Kiyofumi},
 book = {宇宙航空研究開発機構特別資料: 第48回流体力学講演会/第34回航空宇宙数値シミュレーション技術シンポジウム論文集, JAXA Special Publication: Proceedings of the 48th Fluid Dynamics Conference / the 34th Aerospace Numerical Simulation Symposium},
 month = {Dec},
 note = {第48回流体力学講演会/第34回航空宇宙数値シミュレーション技術シンポジウム (2016年7月6日-8日. 金沢歌劇座), 金沢市, 石川, 48th Fluid Dynamics Conference /the 34th Aerospace Numerical Simulation Symposium (July 6-8, 2016. The Kanazawa Theatre), Kanazawa, Ishikawa, Japan, Stencil programs, which are mainly used for numerical simulations of continuum dynamics like fluid mechanics, require relatively high memory bandwidth of CPUs. On the other hand, current supercomputers have relatively low memory bandwidth compared to high computational performance of CPUs. It is called a memory wall problem, namely low B/F (Bytes/s per FLOP/s, FLoating OPeration/s) ratio. This paper makes a study on how to increase computational performance of stencil programs on current CPUs whose memory bandwidth is relatively lower. A practical methodology, which can enhance the computational performance, is proposed according to a study of a basic performance of SORA-MA (JAXA's new supercomputer) by a basic benchmark program. This methodology is applied to an actual stencil program, showing an improvement of computational performance by using characteristics of SORA-MA., 形態: カラー図版あり, Physical characteristics: Original contains color illustrations, 資料番号: AA1630031011, レポート番号: JAXA-SP-16-007},
 pages = {101--106},
 publisher = {宇宙航空研究開発機構(JAXA), Japan Aerospace Exploration Agency (JAXA)},
 title = {ステンシル系プログラムの低メモリバンド幅CPU 向け高速化手法の検討},
 volume = {JAXA-SP-16-007},
 year = {2016}
}