@inproceedings{oai:jaxa.repo.nii.ac.jp:00039546,
 author = {Kosuge, Atsutake and Ishizuka, Shu and Abe, Mami and Ichikawa, Satoshi and Kuroda, Tadahiro},
 book = {Solid- State Circuits Conference - (ISSCC), 2015 IEEE International},
 month = {Feb},
 note = {Solid- State Circuits Conference - (ISSCC), 2015 IEEE International  (February 22-26, 2015.), San Francisco, CA, USA, Processor systems that are mounted in satellites must be small and light, having high data transfer rates, and high storage capacity [1]. A small reduction in size and weight could reduce the cost of launching a satellite by a significant amount. The next generation of earth observation satellites will require data transmission rates to a maximum of 20Gb/s and at least one terabyte of storage capacity. The volume, weight, and communication speed of the processor system is determined by the backplane connectors (Fig. 20.4.1). It is difficult to achieve a connector that can pass signals of 2.5Gb/s or more. The signal reflection that occurs when signals are branched at connectors and at the wire stubs of branches decreases the transmission speed, so only point-to-point connections are possible. Once the satellite is launched, repair or replacement is not possible, and system redundancy is introduced. Accordingly, 512 backplane wires would be required. The signal connector would require 1,024pins, including the ground pins used to prevent crosstalk, and would be 512mm wide, which is even wider than the circuit board of each module., 資料番号: PA1510077000},
 pages = {1--3},
 publisher = {Institute of Electrical and Electronics Engineers, Inc.(IEEE)},
 title = {24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%},
 year = {2015}
}