@inproceedings{oai:jaxa.repo.nii.ac.jp:00004326,
 author = {Ibe, Eishi and Shimbo, Kenichi and Toba, Tadanobu and Taniguchi, Hitoshi and Uezono, Takumi and Nishii, Koji and Taniguchi, Yoshio and Ibe, Eishi and Shimbo, Kenichi and Toba, Tadanobu and Taniguchi, Hitoshi and Uezono, Takumi and Nishii, Koji and Taniguchi, Yoshio},
 book = {宇宙航空研究開発機構特別資料, JAXA Special Publication},
 month = {Mar},
 note = {Abstract-As semiconductor device scaling is on-going far below 100nm design rule, terrestrial neutron-induced soft-error typically in CMOS devices is predicted to be worsen furthermore. Moreover, novel failure modes that may be more serious than those in memory soft-error are recently being reported. Therefore, necessity of implementing mitigation techniques is rapidly growing at the design phase, together with development of advanced detection and quantification techniques. The most advanced such techniques are reviewed and discussed., 形態: カラー図版あり, Physical characteristics: Original contains color illustrations, 資料番号: AA0061889032, レポート番号: JAXA-SP-12-008E},
 pages = {148--154},
 publisher = {宇宙航空研究開発機構(JAXA), Japan Aerospace Exploration Agency (JAXA)},
 title = {State-of-the-Art Study on Mitigation Techniques of Single Event Effects in Terrestrial Applications},
 volume = {JAXA-SP-12-008E},
 year = {2013}
}