@techreport{oai:jaxa.repo.nii.ac.jp:00006298,
 author = {山田, 理子 and 新藤, 浩之 and 久保山, 智司 and 松田, 純夫 and Yamada, Noriko and Shindo, Hiroyuki and Kuboyama, Satoshi and Matsuda, Sumio},
 month = {Jan},
 note = {Several failures of a new generation of Antifuse type FPGAs (RTSX-S, SX-A) were reported subsequent to successful programming in the U.S. in 2003. It was inferred that the degradation of Antifuses causes the signal delay after the investigations and evaluations performed by NASA, Industry Tiger Team (ITT) and so forth. It was also suggested that the structure of FPGA die produced by MEC (Matsushita Electric Corp.) has an internal defect. The manufacturer recommends exchange to UMC die devices which are functionally compatible with MEC die devices. These devices are used by nearly several programs in JAXA with recently built hardware. Rapid identification of root-cause and remediation are needed to keep programs on schedule. The evaluation of Antifuse type FPGAS has been started at the beginning of 2005 in JAXA. In FY 2004, evaluation test preparation (the design of FPGA circuit and the program for an electrical parameter test) and the initial evaluation test to A54SX32A were carried out. The signal delay caused by antifuse degradation was successfully detected., 資料番号: AA0049054042, レポート番号: JAXA-SP-05-008},
 title = {アンチヒューズ型FPGAの評価試験結果},
 year = {2006}
}