{"created":"2023-06-20T14:39:33.346495+00:00","id":6298,"links":{},"metadata":{"_buckets":{"deposit":"1c48085f-28ac-4d9f-902c-16b03a72e786"},"_deposit":{"created_by":1,"id":"6298","owners":[1],"pid":{"revision_id":0,"type":"depid","value":"6298"},"status":"published"},"_oai":{"id":"oai:jaxa.repo.nii.ac.jp:00006298","sets":["1887:1893","9:789:1031:1060"]},"author_link":["31802","31801","31800","31803","31804","31805","31799","31806"],"item_3_alternative_title_2":{"attribute_name":"その他のタイトル（英）","attribute_value_mlt":[{"subitem_alternative_title":"Evaluation results of Antifuse type FPGA"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2006-01-20","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"206","bibliographicPageStart":"201","bibliographicVolumeNumber":"JAXA-SP-05-008","bibliographic_titles":[{"bibliographic_title":"宇宙航空研究開発機構特別資料: 平成16年度総合技術研究本部宇宙領域宇宙科学研究本部合同研究成果報告書:人工衛星系基盤技術"},{"bibliographic_title":"JAXA Special Publication: FY2004 Report of Joint Research Achievements of the Space Division of Institute of Aerospace Technology and Institute of Space and Astronautical Science: Basic Technologies of Satellite Systems","bibliographic_titleLang":"en"}]}]},"item_3_description_17":{"attribute_name":"抄録（英）","attribute_value_mlt":[{"subitem_description":"Several failures of a new generation of Antifuse type FPGAs (RTSX-S, SX-A) were reported subsequent to successful programming in the U.S. in 2003. It was inferred that the degradation of Antifuses causes the signal delay after the investigations and evaluations performed by NASA, Industry Tiger Team (ITT) and so forth. It was also suggested that the structure of FPGA die produced by MEC (Matsushita Electric Corp.) has an internal defect. The manufacturer recommends exchange to UMC die devices which are functionally compatible with MEC die devices. These devices are used by nearly several programs in JAXA with recently built hardware. Rapid identification of root-cause and remediation are needed to keep programs on schedule. The evaluation of Antifuse type FPGAS has been started at the beginning of 2005 in JAXA. In FY 2004, evaluation test preparation (the design of FPGA circuit and the program for an electrical parameter test) and the initial evaluation test to A54SX32A were carried out. The signal delay caused by antifuse degradation was successfully detected.","subitem_description_type":"Other"}]},"item_3_description_32":{"attribute_name":"資料番号","attribute_value_mlt":[{"subitem_description":"資料番号: AA0049054042","subitem_description_type":"Other"}]},"item_3_description_33":{"attribute_name":"レポート番号","attribute_value_mlt":[{"subitem_description":"レポート番号: JAXA-SP-05-008","subitem_description_type":"Other"}]},"item_3_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宇宙航空研究開発機構"}]},"item_3_publisher_9":{"attribute_name":"出版者（英）","attribute_value_mlt":[{"subitem_publisher":"Japan Aerospace Exploration Agency (JAXA)"}]},"item_3_source_id_21":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1349-113X","subitem_source_identifier_type":"ISSN"}]},"item_3_source_id_24":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11984031","subitem_source_identifier_type":"NCID"}]},"item_3_text_6":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"宇宙航空研究開発機構 総合技術研究本部"},{"subitem_text_value":"宇宙航空研究開発機構 総合技術研究本部"},{"subitem_text_value":"宇宙航空研究開発機構 総合技術研究本部"},{"subitem_text_value":"宇宙航空研究開発機構 総合技術研究本部"}]},"item_3_text_7":{"attribute_name":"著者所属（英）","attribute_value_mlt":[{"subitem_text_language":"en","subitem_text_value":"Japan Aerospace Exploration Agency Institute of Space Technology and Aeronautics"},{"subitem_text_language":"en","subitem_text_value":"Japan Aerospace Exploration Agency Institute of Space Technology and Aeronautics"},{"subitem_text_language":"en","subitem_text_value":"Japan Aerospace Exploration Agency Institute of Space Technology and Aeronautics"},{"subitem_text_language":"en","subitem_text_value":"Japan Aerospace Exploration Agency Institute of Space Technology and Aeronautics"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山田, 理子"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"新藤, 浩之"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"久保山, 智司"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松田, 純夫"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yamada, Noriko","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shindo, Hiroyuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kuboyama, Satoshi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Matsuda, Sumio","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-01-16"}],"displaytype":"detail","filename":"49054042.pdf","filesize":[{"value":"1.5 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"49054042.pdf","url":"https://jaxa.repo.nii.ac.jp/record/6298/files/49054042.pdf"},"version_id":"c6482fbf-2c23-4670-a448-bad4559936cd"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アンチヒューズ型FPGA","subitem_subject_scheme":"Other"},{"subitem_subject":"宇宙機電子機器","subitem_subject_scheme":"Other"},{"subitem_subject":"不具合","subitem_subject_scheme":"Other"},{"subitem_subject":"部品信頼性","subitem_subject_scheme":"Other"},{"subitem_subject":"集積回路","subitem_subject_scheme":"Other"},{"subitem_subject":"LSI","subitem_subject_scheme":"Other"},{"subitem_subject":"ダイデバイス","subitem_subject_scheme":"Other"},{"subitem_subject":"集積回路","subitem_subject_scheme":"Other"},{"subitem_subject":"antifuse type FPGA","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"spacecraft electronic equipment","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"malfunction","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"component reliability","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"integrated circuit","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"LSI","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"die device","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"evaluation test","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"technical report","resourceuri":"http://purl.org/coar/resource_type/c_18gh"}]},"item_title":"アンチヒューズ型FPGAの評価試験結果","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"アンチヒューズ型FPGAの評価試験結果"}]},"item_type_id":"3","owner":"1","path":["1060","1893"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-03-26"},"publish_date":"2015-03-26","publish_status":"0","recid":"6298","relation_version_is_last":true,"title":["アンチヒューズ型FPGAの評価試験結果"],"weko_creator_id":"1","weko_shared_id":-1},"updated":"2023-06-21T07:58:14.194318+00:00"}