@techreport{oai:jaxa.repo.nii.ac.jp:00006300,
 author = {新藤, 浩之 and 浅井, 弘彰 and 池田, 直美 and 山田, 理子 and 久保山, 智司 and 松田, 純夫 and Shindo, Hiroyuki and Asai, Hiroaki and Ikeda, Naomi and Yamada, Noriko and Kuboyama, Satoshi and Matsuda, Sumio},
 month = {Jan},
 note = {Hardness-By-Design (HBD) approach for 0.15 micrometer fully depleted CMOS/SOI process was studied. We designed logic cells hardened for SEU/SET and performed the irradiation tests in order to evaluate the effectiveness of this methodology. Excellent hardness was achieved, and it is thought that state-of-the-art parts can be applied to space by using this technique., 資料番号: AA0049054044, レポート番号: JAXA-SP-05-008},
 title = {民生部品を生かすHBD技術},
 year = {2006}
}