| Item type |
学術雑誌論文 / Journal Article(1) |
| 公開日 |
2015-03-26 |
| タイトル |
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|
タイトル |
Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA |
|
言語 |
en |
| 言語 |
|
|
言語 |
eng |
| キーワード |
|
|
言語 |
en |
|
主題Scheme |
Other |
|
主題 |
computational fluid dynamics (CFD) |
| キーワード |
|
|
言語 |
en |
|
主題Scheme |
Other |
|
主題 |
field programmable gate array (FPGA) |
| キーワード |
|
|
言語 |
en |
|
主題Scheme |
Other |
|
主題 |
scientific computations |
| キーワード |
|
|
言語 |
en |
|
主題Scheme |
Other |
|
主題 |
reconfigurable hardware |
| キーワード |
|
|
言語 |
en |
|
主題Scheme |
Other |
|
主題 |
partial reconfiguration |
| 資源タイプ |
|
|
資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
|
資源タイプ |
journal article |
| 著者 |
Abu, Talip Mohamad Sofian
赤嶺, 高之
長名, 保範
藤田, 直行
天野, 英晴
Abu, Talip Mohamad Sofian
Akamine, Takayuki
Osana, Yasunori
Fujita, Naoyuki
Amano, Hideharu
|
| 著者所属 |
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慶應義塾大学大学院理工学研究科 |
| 著者所属 |
|
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慶應義塾大学大学院理工学研究科 |
| 著者所属 |
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琉球大学工学部電気電子工学科 |
| 著者所属 |
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宇宙航空研究開発機構航空本部数値解析技術研究グループ(JAXA) |
| 著者所属 |
|
|
|
慶應義塾大学大学院理工学研究科 |
| 著者所属（英） |
|
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|
en |
|
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Graduate School of Science and Technology, Keio University |
| 著者所属（英） |
|
|
|
en |
|
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Graduate School of Science and Technology, Keio University |
| 著者所属（英） |
|
|
|
en |
|
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Department of Electrical and Electronics Engineering, University of the Ryukyus |
| 著者所属（英） |
|
|
|
en |
|
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Numerical Simulation Research Group, Institute of Aeronautical Technology, Japan Aerospace Exploration Agency (JAXA) |
| 著者所属（英） |
|
|
|
en |
|
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Graduate School of Science and Technology, Keio University |
| 出版者 |
|
|
出版者 |
電子情報通信学会 |
| 出版者（英） |
|
|
出版者 |
The Institute of Electronics, Information and Communication Engineers |
| 書誌情報 |
en : IEICE TRANSACTIONS on Information and Systems
巻 E95-D,
号 10,
p. 2369-2376,
発行日 2012-10-01
|
| 抄録（英） |
|
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内容記述タイプ |
Other |
|
内容記述 |
Computational Fluid Dynamics (CFD) is used as a common design tool in the aerospace industry. UPACS, a package for CFD, is convenient for users, since a customized simulator can be built just by selecting desired functions. The problem is its computation speed, which is difficult to enhance by using the clusters due to its complex memory access patterns. As an economical solution, accelerators using FPGAs are hopeful candidate. However, the total scale of UPACS is too large to be implemented on small numbers of FPGAs. For cost efficient implementation, partial reconfiguration which dynamically loads only required functions is proposed in this paper. Here, the MUSCL scheme, which is used frequently in UPACS, is selected as a target. Partial reconfiguration is applied to the flux limiter functions (FLF) in MUSCL. Four FLFs are implemented for Turbulence MUSCL (TMUSCL) and eight FLFs are for Convection MUSCL (CMUSCL). All FLFs are developed independently and separated from the top MUSCL module. At start-up, only required FLFs are selected and deployed in the system without interfering the other modules. This implementation has successfully reduced the resource utilization by 44% to 63%. Total power consumption also reduced by 33%. Configuration speed is improved by 34-times faster as compared to full reconfiguration method. All implemented functions achieved at least 17 times speed-up performance compared with the software implementation. |
| ISSN |
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収録物識別子タイプ |
ISSN |
|
収録物識別子 |
0916-8532 |
| ISSNONLINE |
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収録物識別子タイプ |
ISSN |
|
収録物識別子 |
1745-1361 |
| 書誌レコードID |
|
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収録物識別子タイプ |
NCID |
|
収録物識別子 |
AA10826272 |
| DOI |
|
|
関連タイプ |
isIdenticalTo |
|
|
識別子タイプ |
DOI |
|
|
関連識別子 |
http://dx.doi.org/10.1587/transinf.E95.D.2369 |
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|
関連名称 |
info:doi/10.1587/transinf.E95.D.2369 |
| 権利 |
|
|
権利情報 |
(C)2012 The Institute of Electronics, Information and Communication Engineers |
| 著者版フラグ |
|
|
出版タイプ |
VoR |
|
出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
| 資料番号 |
|
|
内容記述タイプ |
Other |
|
内容記述 |
資料番号: PA1210022000 |
PA2012022.pdf (693.6 kB)
